The HEVC HD Decoder Core by VYUsync is a highly optimized video decompression engine targeted primarily at FPGAs. The decoder achieves real-time performance for high definition (HD) video with ultra-low latency & optimized resource utilization. It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics.
The decoder design is fully autonomous and does notrequire any external processor to aid the decode operation.The IO interface comprises of an input FIFO and an outputframe buffer. Decoded data can also be provided on a serialbus with embedded sync information. The decoder requiresDDR SDRAM to store reference pictures.
The decoder solution is available either as a FPGA netlist orin source code format and can be customized to meet therequirements of end users.
