CoreEL is a well known, professionally managed, high end Customer Application Specific Product and Solutions (CASPS) company, providing engineering turnkey services & products to its clients worldwide in the areas of Electronic Systems Development, FPGA/RTL/ASIC development, Firmware/BSP/API/GUI/Application development & PCB CAD along with manufacturing; servicing Broadcasting, Medical, Telecom, Networking, Industrial, Defence & Aerospace market segments.
CoreEL is a “Xilinx Premier Member” & among first 3 companies selected world-wide when program was launched.
CoreEL is ISO: 9001:2008 & CEMILAC (Centre for Military Airworthiness and Certification) certified and has robust proven methodologies for engineering development. There are well documented, strictly adhered processes and guidelines for documentation, coding, verification, reviews and deliveries.
CoreEL’s solutions for the high-end video broadcast industry are among the best in the world. Over 70% of the top-tier video broadcast equipment manufacturers have licensed CoreEL’s intellectual properties for their products. In last 8 years, customers have shipped more than 50,000 units with CoreEL IP. Our video customer base spreads across various industries worldwide such as Broadcast, Professional Audio-Video (AV), Digital Cinema, Medical, Automotive, Aerospace & Defence, Security & Surveillance.
CoreEL’s Intra Frame Codec is one of industry’s first FPGA based single chip I-Frame only encoding and decoding solutions.
CoreEL H.264 Intra frame encoder / decoder is available for both Xilinx and Altera FPGA cores. The Codec IP is optimised for very low latency applications. The codec solution is a single FPGA solution which is highly pipelined video solution.
The Codec design is fully autonomous. It does not require any external processor to aid the codec operations.This Codec IP hence would be used in Ingest/Archiving Video Servers, RF video links, ISM video applications and 3D video.
The H.264 Intra Frame codec IP has the following features:
- High profile coding
- Also supports Main & Constrained Baseline Profile
- Bit depth up to 10 bits
- 4:2:0 and 4:2:2 Chroma format
- Supports resolutions up to Full HD (1920x1080p60) and 4Kp60
- Supports progressive and interlaced formats for HD resolutions
- High Bitrate support
- Single Chip FPGA solution
- Simultaneous multi-channel encode-decode
- Rate Distortion Optimisation
- Dual Pass encoding
- CBR, VBR and Capped VBR rate control
- Ultra low delay encoding mode
- Supports both CABAC & CAVLC Entropy coding
- Support for mathematically lossless coding in CAVLC entropy mode
MPEG-2 Video codec is still an important codec in the capacity of legacy products already existing in great numbers in the market. CoreEL MPEG-2 IP core is compliant with ISO/IEC 13818-2 standards (also standardised by ITU-T as H.262). The decoder solution is available both as FPGA Netlist and Source code.
- Broadcast and Professional Video
- Video Distribution
- Multi-format digital receivers
- Test & Measurement
- Medical, Aerospace & Defence
The AVC Intra Decoder is implemented on FPGA devices targeting high definition, high quality and high bit-rate application segments. The IP core supports the H.264 / MPEG-4 Part-10 Advanced Video Coding standard and has been optimised for lower memory footprints and higher performance.
The decoder core is compliant with ISO / IEC 14496-10 standard and ITU-T H.264 standard and adheres to SMPTE specification RP 2027-2012 for AVC Intra Class 50 and Class 100 specifications.
CoreEL’s decoder design implementation is a highly pipelined architecture for faster I-frame processing. The decoder is easily portable across various FPGA platforms. The IP core has been validated with JVT and Panasonic test streams on Xilinx Virtex-5 / Virtex-6 & Kintex-7 FPGA devices.
The decoder design is fully autonomous and does not require external host processor for decoder to perform. The decoder solution is available both as FPGA netlist and Source code. The core supports very high bit-rate implementations.
The H.264 Hi422 High Performance Decoder IP Core is a highly optimised, pipelined video decompression engine supporting H.264 / MPEG-4 Part 10 standards. It is compliant with ISO/IEC 14496-10, 2005 standards and ITU-T H.264 standards.
The high performance solution is designed for scalability and modularity, targeting high end video contribution and professional video applications.
- Broadcast & Professional Video
- Broadcast Contribution & Distribution
- Video Servers
- Test & Measurements
- Aerospace & Defence
The HEVC Decoder Core is a highly optimised, pipelined video decompression engine supporting the H.265/MPEG-H Part 2 standard. It is compliant with the ISO/ IEC 23008-2 standard and ITU-T H.265 standard.
The decoder solution is designed for scalability and modularity, targeting various applications ranging from High End Broadcast and Professional Video to high end consumer electronics application.
- Main Profile,Main4:2:2 10 Profile up to Main 4:4:4 12 Profile and respective Intra profiles
- Support for Level 4.1 High tier (upto 50 Mbps) and scalable to high bitrates
- Resolution support up to 1920x1080p60 and 4096x2160p60
- Chroma format support up to 4:2:2& 4:4:4
- Colour Bit depth support up to 10 &12-bits
- Single Chip FPGA solution
- Optimised resource foot print
CoreEL SMPTE 2022-5/6/7 IP cores provide solutions for transporting Uncompressed Video (SDI) over IP. SMPTE 2022-5, 2022-6 & 2022-7 can be configured independently based on the application
SMPTE 2022-5 : Forward Error Correction (FEC) for SMPTE 2022-6 IP Packets
SMPTE 2022-6 : Transport of High Bit Rate Media Signals over IP Networks
SMPTE 2022-7 : Seamless Protection Switching of RTP Datagrams
- Real-time audio/video applications
- Streaming live IP camera views
- Professional broadcast contribution and primary distribution
- Studio-to-studio media exchange
- Transport uncompressed audio, video, ancillary streams over IP networks
The ST 2110 IP suite is comprised of both Packetizer (Video/Audio/ANC to IP) and De-Packetizer (IP to Video/Audio/ANC) modules,
supporting the following standards
ST 2110-10: System Timing and Definitions
ST 2110-20: Uncompressed Active Video
ST 2110-21: Traffic Shaping and Delivery Timing for Video
ST 2110-30: PCM Digital AudioST 2110-40: Transport of SMPTE Ancillary Data
CoreEL’s Video IP portolio also includes SMPTE ST 2022-5/6/7 IP cores and SMPTE ST 2022-6 to SMPTE ST 2110 bridge, to support ST
2022 contribution feed coming to a ST 2110 studio.
• Supports PTP slave configuration, for synchronization of audio, video and other essence, to IEEE 1588 (PTP) grandmaster.
• Supports AMWA NMOS (IS-04 and IS-05) based RESTful API, to ensure interoperability with any other control system for network
management and control.
• PTP stack and NMOS implementation on Processor
• Provides synchronization pulse for external clock recovery mechanism
• Supports 1G/10G Ethernet Interface
• Supports User Configuration over AXI4-Lite interface
• Supports AXI4-Memory Interface for External memory access
• Supports AXI4-Stream Interface for Video, Audio and Ancillary data
• Supports Statistics and Debug features
• Seamless integration with CoreEL’s SMPTE 2022-7 IP core, for Seamless Protection Switching feature